1. Field of the Invention
This invention relates generally to ferroelectric memories. More particularly, the present invention relates to those memories employing an array of one-transistor, one-capacitor ("1T/1C") ferroelectric memory cells.
2. Related Application Information
This application is related to the following applications filed concurrently herewith and also assigned to the assignee of the present invention, which are all hereby specifically incorporated by this reference:
Ser. No. 08/970,452, entitled "REFERENCE CELL FOR A 1T/1C FERROELECTRIC MEMORY"; PA1 Ser. No. 08/970,520, entitled "MEMORY CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY"; PA1 Ser. No. 08/970,518, entitled "REFERENCE CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY"; PA1 Ser. No. 08/970,519, entitled "SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY"; PA1 Ser. No. 08/970,454, entitled "COLUMN DECODER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY"; PA1 Ser. No. 08/970,521, entitled "SENSE AMPLIFIER LATCH DRIVER CIRCUIT FOR A 1T/ 1C FERROELECTRIC MEMORY"; PA1 Ser. No. 08/970,453, now U.S. Pat. No. 5,880,989, issued Mar. 9,1999, entitled "SENSING METHODOLOGY FOR A 1T/1C FERROELECTRIC MEMORY"; and PA1 Ser. No. 08/970,448, entitled "PLATE LINE SEGMENTATION IN A 1T/1C FERROELECTRIC MEMORY".